FPGA Implementation and Validation of the Asynchronous Array of simple Processors

In today’s ASIC market validating a VLSI design in a field programmable gate array (FPGA) device before tape out can save a significant amount of time and therefore, money up front in the design process. At the University of California, Davis, we are working on the design of a highly parallel, reconfigurable processor chip, known as the Asynchronous Array of simple Processors (AsAP). This report will summarize my design approach and results in both implementing and validating the AsAP processor in a Xilinx Spartan 3 FPGA.